Memory devices conventionally include arrays of bit cells that each store a bit of data. Each data bit can represent a logical zero (“0”) or a logical one (“1”), which may correspond to a state of the bit cell. During a read operation of a selected bit cell, a low voltage level represents a logical “0” and a relatively higher voltage level represents a logical “1”.
FIG. 1 illustrates a conventional six-transistor static random-access memory (6T SRAM) bit cell 100. The bit cell 100 comprises a pair of cross-coupled inverters, each cross-coupled inverter comprising a p-channel metal oxide semiconductor (PMOS) pull-up transistor and an n-channel metal oxide semiconductor (NMOS) pull-down transistor separated by a storage node. The first inverter comprises a first storage node 110 which stores a first logical value. The first storage node 110 is arranged between a first pull-up transistor 112 and a first pull-down transistor 114. The second inverter comprises a second storage node 120 which stores a second logical value. The second storage node 120 is arranged between a second pull-up transistor 122 and a second pull-down transistor 124. When the pair of inverters are cross-coupled, the first logical value is the opposite or inverse of the second logical value.
In a read operation of bit cell 100, the bit line 150 and bit line 160 are both pre-charged. Then the word line 170 is set to a high-voltage state in order to select bit cell 100, which turns on transistors 152 and 162. If the 6T SRAM bit cell 100 stores a logical “1,” without loss of generality, a logical “1” appears at the first storage node 110 of the first inverter and a logical “0” appears at the second storage node 120 of the second inverter. By turning on the access transistors 152 and 162 the voltage on the bit line 150 will be maintained by the pull-up transistor 112, whereas the voltage on the bit line 160 will be discharged by the pull-down transistor 124. Sense amplifiers (not shown) are used to amplify the differential voltage which appears on bit line 150 and bit line 160, and a logical value of “1” is read. On the other hand, if a logical “0” is stored in bit cell 100, a logical “0” appears at the first storage node 110 and a logical “1” appears at the second storage node 120. Reading bit cell 100 results in the opposite of the above process, in the sense that bit line 150 will be discharged and bit line 160 will remain charged to a high voltage, eventually leading to a logical value of “0” being read.
In a write operation of bit cell 100, for the case of writing a logical “1,” bit line 150 is driven to a high-voltage state, and bit line 160 is driven to a low-voltage state. Then the word line 170 is set to a high-voltage state to select bit cell 100, which turns on access transistors 152 and 162. Since the bit line 150 is in a high-voltage state, a logical “1” will be written to the first storage node 110 and, since the bit line 160 is in a low-voltage state, a logical “0” will be written to the second storage node 120. For the write of a logical “0,” the opposite process is followed, in the sense that bit line 160 will be driven to a high-voltage state and the bit line 150 will be driven to a low-voltage state.
As memory devices become smaller, a problem arises in that their reliability and performance decrease. For example, a static noise margin (SNM) is defined as the minimum noise voltage (as measured between the first storage node 110 and the second storage node 120) which is capable of inadvertently flipping the state of the bit cell. A read static noise margin (RSNM) is defined as the amount of noise voltage capable of inadvertently flipping the state of the bit cell during a read operation of the bit cell. As bit cells become smaller, size constraints can reduce the RSNM of the bit cells, causing them to become more sensitive to noise resulting from, for example, temperature changes or process variations.
FIG. 2 illustrates a conventional eight-transistor static random-access memory (8T SRAM) bit cell 200. In bit cell 200, the data storage nodes 210 and 220, analogous to the storage nodes 110 and 120 of a conventional 6T SRAM bit cell such as bit cell 100, are decoupled from a read bit line 282 using decoupling transistors 280 and 290. Because the read bit line 282 is decoupled from the data storage nodes 210 and 220, a read operation is much less likely to cause an inadvertent flipping of the state of the bit cell. Thus, the RSNM of bit cell 200 is higher than or equal to a hold SNM (HSNM) which pertains to the noise margin when no active read/write operation is in progress for bit cell 200. However, since the bit cell 200 consists of two extra decoupling transistors 280 and 290, the area of the bit cell increases.
Moreover, in addition to the read bit line 282, the bit cell 200 includes a read word line 272 which is activated for read operations on the bit cell 200. Further, the bit cell 200 comprises separate write bit lines 250 and 260 and a separate write word line 270 for write operations. The write bit lines 250 and 260 are analogous to the bit lines 150 and 160 of bit cell 100, except that they are not used during a read operation. Similarly, the write word line 270 is analogous to the word line 170 of bit cell 100, except that the write word line 270 is not used during a read operation.
A further advantage of the 8T SRAM of FIG. 2 is that different transistors are used for read and write operations. Because different transistors are used for read and write operations, the respective transistors can be independently optimized. For example, write speed can be improved by strengthening the write access transistors 252 and 262. However, strengthening the write access transistors can create a problem where a write operation on a target bit cell can affect not only the target bit cell, but also every other cell in the target bit cell's row. The write operation can affect the whole row because the write word line is disposed in a row direction of the memory array (i.e., each bit cell in a given row of the memory array shares a single write word line). This problem, known as the “half-select” problem, can impair the reliability of a write-speed-optimized 8T SRAM such as the one depicted in FIG. 2.
One proposed solution to the half-select problem in 8T SRAM is a write-back scheme employed for write operations. In a write-back scheme, every bit cell in a row is first read to determine a stored value. The stored value is then modified based on the data to be written, and this modified value is written back to all the bit cells, including one or more target bit cells. By performing a write operation on every bit cell in a row containing the one or more target bit cells, the write-back scheme avoids the problem of inadvertently causing a disturbance in a bit cell which merely shares a row with a target bit cell.
However, a write-back scheme has its own drawbacks. Particularly, power consumption increases because both read and write operations are performed for an entire row for every write cycle.
Accordingly, there is a need for improving noise margins and data stability of bit cells while avoiding the aforementioned drawbacks of the conventional approaches.